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MC100EPT23 Dual Differential LVPECL to LVTTL Translator
The MC100EPT23 is a dual differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the dual gate design of the EPT23 makes it ideal for applications which require the translation of a clock and a data signal. The EPT23 is available in only the ECL 100K standard. Since there are no LVPECL outputs or an external VBB reference, the EPT23 does not require both ECL standard versions. The LVPECL inputs are differential. Therefore, the MC100EPT23 can accept any standard differential LVPECL input referenced from a VCC of +3.3V.
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8 1 SO-8 D SUFFIX CASE 751
* * * * * * * * * * * *
1.5ns Typical Propagation Delay Minimum Operating Frequency > 275MHz Differential LVPECL Inputs Small Outline SOIC Package 24mA LVTTL Outputs Flow Through Pinouts Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D Q Output will default LOW with inputs open or at GND ESD Protection: >1.2KV HBM, >150V MM Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 91 devices
MARKING DIAGRAM
8 KPT23 ALYW 1 *For additional information, see Application Note AND8002/D A L Y W = Assembly Location = Wafer Lot = Year = Work Week
PIN DESCRIPTION
PIN Q0, Q1 D0, D1, D0, D1 FUNCTION LVTTL Outputs Differential LVPECL Inputs Positive Supply Ground
D0 1
8
VCC
VCC GND
D0
2 LVPECL LVTTL
7
Q0
D1
3
6
Q1
ORDERING INFORMATION
Device Package SOIC SOIC Shipping 98 Units/Rail 2500 Tape & Reel
D1
4
5
MC100EPT23D
GND
MC100EPT23DR2
Figure 1. 8-Lead Pinout and Logic Diagram
(c) Semiconductor Components Industries, LLC, 1999
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September, 1999 - Rev. 1.0
Publication Order Number: MC100EPT23/D
MC100EPT23
MAXIMUM RATINGS*
Symbol VCC VI Iout TA Tstg JA JC Tsol Parameter Power Supply (GND = 0V) Input Voltage (GND = 0V, VI not more positive than VCC) Output Current Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Value 0 to 3.8 0 to 3.8 50 100 -40 to +85 -65 to +150 190 130 41 to 44 5% 265 Unit VDC VDC mA C C C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur.
DC CHARACTERISTICS (VCC = 3.3V 0.3V; GND = 0V; TA = -40C to 85C)
Symbol ICCH ICCL VIH VIL IIH IIL VOH VOL IOS Characteristic Power Supply Current (Outputs set to HIGH) Power Supply Current (Outputs set to LOW) Input HIGH Voltage (VCC = 3.3) (Note 1.) Input LOW Voltage (VCC = 3.3) (Note 1.) Input HIGH Current Input LOW Current Output HIGH Voltage (IOH = -3.0mA) (Note 2.) Output LOW Voltage (IOL = 24mA) (Note 2.) Output Short Circuit Current -180 D D -150 2.4 0.5 -50 V V mA Min 10 15 2135 1490 Typ 18 26 Max 25 33 2420 1825 150 0.5 Unit mA mA mV mV A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 3.) 2.0 3.3 V NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. All values vary 1:1 with VCC. 2. All loading with 500 ohms to GND, CL = 20pF. 3. VIHCMR min varies 1:1 with GND, max varies 1:1 with VCC.
AC CHARACTERISTICS (VCC = 3.3V 0.3V; GND = 0V)
-40C Symbol fmax tPLH, tPHL tSK+ + tSK- - tSKPP tJITTER VPP tr tf 4. 5. 6. 7. Characteristic Maximum Toggle Frequency (Note 4.) Propagation Delay to Output Differential (Note 5.) Output-to-Output Skew++ Output-to-Output Skew- - Part-to-Part Skew (Note 6.) Cycle-to-Cycle Jitter Input Voltage Swing (Differential) (Note 7.) Output Rise/Fall Times (20% - 80%) Q, Q 100 330 Min 275 1.2 1.2 Typ 350 1.5 1.5 60 25 500 TBD 800 600 1200 900 100 330 1.8 1.8 Max Min 275 1.2 1.2 25C Typ 350 1.5 1.5 60 25 500 TBD 800 600 1200 900 100 330 1.8 1.8 Max Min 275 1.3 1.2 85C Typ 350 1.7 1.5 60 25 500 TBD 800 650 1200 900 2.2 1.8 Max Unit MHz ns ps
ps mV ps
Fmax guaranteed for functionality only. VOL and VOH levels are guaranteed at DC only. Reference (VCC = 3.3V 5%; GND = 0V) Skews are measured between outputs under identical conditions. 200mV input guarantees full logic swing at the output.
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MC100EPT23
PACKAGE DIMENSIONS
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-06 ISSUE T
A
8
D
5
C
E
1 4
H
0.25
M
B
M
h B C e A
SEATING PLANE
X 45 _
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_
q
L 0.10 A1 B 0.25
M
CB
S
A
S
q
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MC100EPT23
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MC100EPT23/D

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